Phase detector

ABSTRACT

The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A trasnsition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector includes first signal generator for generating a first binary signal ERRQ a second signal generator for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ΔT 2  between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA.

Clock and data recovery (CDR) is a critical function in high-speedtransceivers. Such transceivers serve in many applications includingoptical communications. The data received in these systems are bothasynchronous and noisy requiring, that a clock be abstracted to allowsynchronized operations. Furthermore, the data must be “retimed” suchthat the jitter accumulated during transmission is removed.

In order to perform synchronous operations such as retiming anddemultiplexing on random data the high-speed transceivers must generatea clock. As illustrated in FIG. 1, a clock recovery circuit senses thedata and produces a periodic clock. A D-flipflop (DFF) driven by theclock then retimes the data, i.e. it samples the noisy data. This yiedsan output with less jitter.

The clock generated in the circuit of FIG. 1 must satisfy threeimportant conditions:

-   -   It must have a frequency equal to the data rate. For example, a        data rate of 10 Gb/s translates to a clock frequency of 10 GH        (with a period of 100 ps),    -   The clock must bear a predefined phase relationship with respect        to the data, allowing optimum sampling of the bits by the clock.        If the rising edges of the clock coincide with the midpoint of        each bit, the sampling occurs farthest from the preceeding and        following data transitions. A maximum margin for jitter and        other timing uncertainties may be provided thus,    -   The clock must exhibit a small jitter since it is the principal        contributor to the retimed data jitter.

FIG. 2 shows a conventional clock recovery circuit. The clock recoverycircuit comprises a voltage controlled oscillator VCO, which isresponsible for outputting the clock signal, as shown in FIG. 1. Thetransitions of the clock signal output by the voltage controlledoscillator VCO have to be synchronised with the transitions of the inputrandom data (NRZ data). The circuit shown in FIG. 2 has two parallelfeedback loops. The first one called frequency loop adjusts thefrequency of the voltage controlled oscillator VCO to the frequency ofthe estimated clock of the input data. The frequency loop comprises afrequency detector, a charge pump and a low pass filter (LPF). Thesecond feedback loop of FIG. 2 is a phase loop. The phase loop comprisesa phase detector, a charge pump and a low pass filter LPF. The phasedetector compares the phase of the data transitions (NRZ datatransitions) with the phase of the recovered clock. For a linear phasedetector the pulse width must be proportional to the detected phasedifference. The pulses output by the phase detector are integrated bythe low pass filter LPF and the voltage of this filter drives the finetuning input of the voltage controlled oscillator VCO. The output of thelow pass filter in the phase loop has an amplitude proportional to thephase difference detected by the phase detector. The charge pumpcircuits are needed to ensure a linear charging/discharging of the lowpass filters LPF inside the frequency and phase loops.

At very high speeds the oscillator design is difficult. For this reasonclock and data recovery circuits (CDR-circuits) are made with the inputrandom data (NRZ-data) at full rate but use a voltage control oscillatorVCO running at half the input data rate. This technique also relaxes thespeed requirements of the phase detector and in some RDR-configurationsof the frequency dividers. These data recovery circuits are calledhalf-rate architectures. They require a phase detector that provides avalid output while sensing a full-rate random data stream and ahalf-rate clock. In other words, if the data rate equals 10 Gb/s, thenthe recovered clock frequency is equal to 5 GH (half the data clock).

FIG. 3 a shows a conventional half-rate phase detector. The circuitcomprises two D-flip-flops L1 and L2 as well as an XOR-gate. TheD-inputs of both D-flip-flops L1 and L2 receive the data signal DIN(corresponding to NRZ-data in FIG. 2). The C-input of the D-flip-flop L1is driven by the clock CK (CK corresponds to the recovered clock in FIG.2). The C-input of the D-Flip-Flop L2 is driven by the inverted clockCK. Thus a data transition D_(IN) is only transmitted to the output A ofthe D-flip-flop L1 during the high phase of the clock CK.Correspondingly, the data transition in D_(IN) is only transferred tothe output B of D-flip-flop L2 during a low phase of clock CK. During alow phase of the clock CK the output A of L1 remains unchanged.Correspondingly, the output B of D-flip-flop L2 remains unchanged duringa high phase of the clock CK. Signals A and B are input to an EXOR-gate.D_(out1) is the output the XOR-gate as well as the output of the phasedetector shown in FIG. 3 a. The right hand side of FIG. 3 a shows anexample for the signals of the phase detector. The width of the signalsoutput by D_(out1) corresponds to the time difference between atransition in D_(in) and the next rising or falling edge of the clockCK. The frequency of the clock CK is half the frequency of the dataclock. A clock with twice the frequency of CK has a rising edge at boththe rising and falling edges of CK. Therefore, a transition betweenC_(in) and a rising edge in the double frequency clock may be detectedby determining the distance in time between a transition in D_(in) andthe next transition (rising or falling edge) of the clock CK.

If a transition in D_(in) occurs during the high phase of the clock CK,then the output of L1 (A) outputs this transition immediately. The latchL2 waits until CK is low and then outputs the transition D_(in) (seeFIG. 6). The difference between a DATA transition in D_(in) and thefalling clock of CK is equal to the time, that A and B differ. B_(out1)is equal to one, whenever A and B differ. The length of a signalD_(out1) is equal to the phase difference to be detected.

FIG. 3 b shows a half rate linear phase detector which has beenpresented by J. Savoy and a B. Razari in “high speed CMOS circuits foroptical receivers”, Kluwer Academic Publishers, 2001, ISBN0-7923-7388-X. This circuit is an extension of the Hogge's detector athalf rate. The data D_(in) are sampled at half rate with theD-flip-flops L1 and L2 on both edges of the clock CK. The error betweenthe clock and the data is being measured by the first XOR-gate at theoutputs A and B of L1 and L2. Since D_(out1) is equal to A XOR B, thewidth of the V_(out1) signals is equal to the phase difference to bedetected. The second pair of D-flip-flops L3 and L4 outputs the retimeddata at half rate. One can obtain the full speed data clock aftermultiplexing the outputs of L3 and L4. The second XOR-gate generates thesignal V_(out2) which constitutes a constant pulse, whenever the datasignal has a transition. Its output V_(out3) can be subtracted from theV_(out1) signal to compensate for the situation when data had atransition and the clock CK and data D_(in) are in phase. The timingdiagrams are depicted next to the circuit shown in FIG. 3 b.

The advantage of this architecture consists in its simplicity and in thelesser stringent requirements for the set up and hold times of thesampling latches. Since the two latches L1 and L2 work in an interleavedway, the positive feedback circuit in the latch (D-flip-flop) has moretime for a decision. Another advantage is the possibility to have theretimed data at full rate. This is an important fact for the situation,when a direct conversion receiver (DCR) works as a pure regenerator(repeater) needed to clean up the jittering data. In DCR applicationsthe difficulty comes from the necessity to generate an error signal,whenever data has a transition and keep the same output when notransition is presented. Since the input data is random, it can havelong patterns without transitions, pushing or pulling the voltagecontrol oscillator (VCO) at a different frequency and the completedirect conversion receiver (DCR) out of lock. That is why the phasedetector, which is in insensitive to a data transition densityconstitutes a phase detector keeping the same value at the output whenno transitions occur. At the same time the data is present at half rateat the output A and B. In a demultiplexed situation the two outputs Aand B can be demultiplexed at lower data rates.

The disadvantage of this circuit is obviously the need to wait until thereference signal D_(out2) has settled, in order to generate a phaseerror and a correction signal D_(out1). Besides, in phase lock, thissignal D_(out2) is two times wider than the signal D_(out1). That is whythe D_(out1) signal has to be multiplied by two in order to get a signalwith a zero average.

Ideally a parallel type of operation for the error signal V_(out1) aswell as for the reference signal V_(out2) is desired.

It is object of the present invention, to provide a phase detector,which overcomes the previously mentioned drawbacks of the state of theart.

The problem is solved by a phase detector according to the appendedclaim 1. The phase detector is adapted to detecting a phase differencebetween a data clock DATA-CLK and a reference clock REF-CLK by using adata signal DATA. A transition of the data signal DATA is synchronouswith a transition of the data clock DATA-CLK and the data clock DATA-CLKand the reference clock REF-CLK have the same frequency. The phasedetector comprises a first signal generator 42 for generating a firstbinary signal ERRQ. A pulse width of the first binary signal is equal toa first time difference ΔT1 between a transition of the data signal DATAand a transition of a first reference clock signal CKQ adjacent to thetransition of the data signal DATA. The pulse width of the first binarysignal may represent both the width of a positive or a negative pulse inthe first binary signal. The first signal generator comprises an inputfor receiving the first reference clock signal CKQ and an input forreceiving the data signal DATA. The first reference clock has half thefrequency of the reference clock and is synchronous with the referenceclock. The phase detector further comprises a second signal generator 40for generating a second binary signal ERRI. A pulse width of the secondbinary signal is equal to a second time difference ΔT2 between atransition of the data signal DATA and a transition of the secondreference clock signal CKI adjacent to the transition of the data signalDATA. The pulse width of the second binary signal may represent thewidth of a positive or a negative pulse. The second signal generator 40comprises an input for receiving the data signal DATA and an input forreceiving the second reference signal CKI. In both the first and secondbinary signal a negative pulse as well as a positive pulse may representa logical 1. A logical 0 may be represented by both a positive as wellas a negative pulse. The phase detector comprises an output signalgenerator for generating an output signal representative of the phasedifference between the data clock DATA-CLK and the reference clockREF-CLK. The output signal is equal to ERRQ−2*(ERRQ AND ERRI). ANDrepresents a logical AND-operation. The output is also equal to ERRQ XORERRI−ERRI. XOR represents a logical XOR-operation. Both equations yieldthe same output signals. The output signals may represent both voltageand current pulses. If the first and second binary signals ERRQ and ERRIassume the values 0 and 1, then the output signal may have the values+1, −1 and 0. In this case, the area under the output signal during aperiod of the data clock is equal to the phase difference to bedetected. An integrator may be used in order to convert the pulsesequence of the phase detector into a signal having an amplituderepresentative of the phase difference.

Embodiments of the present invention will be described with reference tothe accompanied drawings below.

FIG. 1 shows a conventional high speed receiver.

FIG. 2 shows a conventional clock recovery circuit.

FIG. 3 shows a conventional half rate phase detector on the left sideand a timing diagram for the signals of the conventional half rate phasedetector on the right side.

FIG. 4 shows another conventional half rate phase detector on the leftside and a timing diagram for the signals of the conventional half ratephase detector on the right side.

FIG. 5 shows an embodiment of a first signal generator and the secondsignal generator of the present invention.

FIG. 6 shows an example for the signals generated in a first and asecond signal generator of FIG. 5.

FIG. 7 shows a further example of the signals generated in the first andsecond signal generators of FIG. 5.

FIG. 8 shows another example of the signals generated in the signalgenerators shown in FIG. 5.

FIG. 9 shows a first embodiment of the present invention.

FIG. 10 shows an example of the signals generated in the firstembodiment of the present invention.

FIG. 11 shows another example of the signals generated in the firstembodiment of the present invention.

FIG. 12 shows a further example of the signals generated in the firstembodiment of the present invention.

FIG. 13 shows a second embodiment of the present invention.

FIG. 14 shows a third embodiment of the present invention.

FIG. 15 shows a fourth embodiment of the present invention.

FIG. 16 shows a fifth embodiment of the present invention.

FIG. 17 shows eight different logical implementations of the phasedetector of FIG. 16.

FIG. 18A shows an XOR-gate, which may be used in the embodiments of thepresent invention.

FIG. 18B shows a logic table of the differential XOR-gate of FIG. 18A.

FIG. 19 shows a NXOR-gate, which may be used in the embodiments of thepresent inventions.

FIG. 20 shows a differential OR-gate, which may be used in theembodiments of the present invention.

FIG. 21 shows a further OR-gate which may be used in the embodiments ofthe present invention.

FIG. 22 shows a phase frequency detector comprising a phase detectoraccording to the present invention.

The first signal generator 42 shown in FIG. 5 comprises a first D-latch(D-flip-flop) L3 and a second D-latch L4 as well as an XOR-gate. Thefirst and second D-latches L3 and L4 each comprise two inputs D and Ckand an output Q. Both inputs D of the first and second D-latch L3 and L4are connected to a line for the data signal. The input Ck of the firstD-latch L3 is connected to the first reference clock signal CKQ and theinput CK of the second latch L4 is connected to the inverted referenceclock signal CKQ. The signal output by the first D-latch L3 is calledX_(1Q) and the signal output by the second D-latch L4 is called X_(2Q).X_(1Q) and X_(2Q) are connected to the inputs of the exclusive OR-gate,which outputs the first binary signal ERRQ. The D-latch L3 istransparent to the data input during the positive level of the clockCKQ. This means, that a change in the data signal is only output to theXOR-gate during a high phase of the reference clock signal CKQ.Inversely, latch L4 is only transparent to the data signal during a lowphase of the clock CKQ. This means, that the first binary signal ERRQ isonly high, if the signals X_(1Q) and X_(2Q) differ. X_(1Q) and X_(2Q)differ, if a transition in the data signal takes place, since only oneof the two latches is transparent to the signal change. Once the firstreference clock signal TKQ makes a transition, the signals X_(1Q) andX_(2Q) have the same value. Consequently, the first binary signal ERRQwill be low. Therefore, the signal output by the XOR-gate have a width,which is equal to the phase difference between the clock CKQ and thedata signal.

The second signal generator 40 for generating a second binary signalERRI shown in FIG. 5 is built in the same way as the first signalgenerator 42 shown in FIG. 5. Instead of the first reference clocksignal CKQ a second reference clock CKI is used. Consequently, thesignal ERRI output by the second binary signal generator has a length,which corresponds to the phase shift between a data transition and atransition in the reference clock signal CKI. The second reference clockCKI is phase shifted with regard to the first reference clock signal CKQby ¼f, wherein f is the frequency of both the first reference clock CKQand the second reference clock CKL.

In FIG. 6, the signals data, CKI, CKQ, X_(1L) and X_(2L), RE, X_(1Q),X_(2Q) and ERRQ are shown on top of each other. The signal DATA shown inFIG. 6 is an example of a DATA signal, received by the reference signalgenerators 40 and 42. The transitions of the DATA signal are synchronouswith a rising edge of a DATA clock. The DATA clock has twice thefrequency of the reference clocks CKI und CKQ. Tb indicated the periodof the DATA clock. The reference clock signals CKI and CKQ are phaseshifted with regard to each other by Tb/2. The first rising edge of theDATA signal occurs during a high phase of the clock CKI. Therefore theoutput X_(1L) of latch L1 is transparent to this DATA signal transition.The DATA signal is output by the second D-latch L2, when the referenceclock signal CKI is low (the reference clock signal CKI is high). Thewidth of the first signal pulse of ERRI shown in FIG. 6 is equivalent tothe distance in time between the first transition of the DATA signal andthe adjacent transition of the reference clock CKI. Correspondingly, thewidth of the signal ERRQ is equal to the distance in time between thetransition of the DATA signal and the next transition of the referenceclock CKQ. FIG. 7 shows the same signals as FIG. 6 for the case, inwhich CKQ is in phase with the DATA transitions. In this case the widthof the signal pulses of ERRI is equal to Tb/2 and the width of thesignal pulses ERRQ is equal to 2*Tb. This is due to the fact, that CKQhas a down transition, whenever data has an up transition, and CKQ hasan up transition, when data has a down transition. The previous remarksare true for the first signal pulses of ERRI and ERRQ. Please note, thatconnecting signals ERRI and ERRQ via an AND-gate yields the signalERRI′. The area under the first two pulses of ERRI′ is equal to half thearea under the first signal pulse of ERRQ. Therefore, ERRQ−2*(ERRI andERRQ) yields a signal representative of the phase difference zero. Thearea under this signal is equal to 0.

FIG. 8 shows another example of the signal generated by the circuitshown in FIG. 5. In this case, the first data transition occurs during ahigh phase of CKQ and during a high phase of CKI. The transition of theCKQ occurs before the down transition of CKL. The phase difference to bedetected is equal to the time difference between the up transition ofthe DATA signal and the down transition of CKQ. Therefore the length ofthe signal pulses shown for ERRQ is equal to the phase difference to bedetected. Connecting ERRI and, ERRQ with and AND-gate yields ERRQ.ERRQ−2(ERRI and ERRQ) yields −ERRQ. The equation also holds for thiscase.

FIG. 9 shows a first embodiment of the present invention. The phasedetector of FIG. 9 comprises the signal generators 40 and 42 shown inFIG. 5. The phase detector further comprises and output signal generator44, which outputs an output signal Pd representative of the phasedifference to be detected. The output signal generator comprises twoinputs connected to the outputs of the first signal generator (42) andthe second signal generator (40). The output signal generator 44comprises and AND-gate, which is connected to the signals ERRI and ERRQfrom the first and second signal generators. ERRI′ constitutes theoutput signal of the AND-gate. This signal is input in a multiplicator,which multiplies the signal by two. The output of the multiplicator *2is input to a summing unit SUM. The summing unit SUM subtracts theoutput of the multiplicator *2 from the first reference signal ERRQ,which is also input to the summing unit. The output signal generator 44constitutes the logical circuit, which corresponds to equationPD=ERRQ−2(ERRI and ERRQ).

FIG. 10 shows the different signals DATA, CKI, CKQ, ERRQ, ERRI′ and PDfor the case, in which CKQ is phase shifted by Tb/2 with regard to thedata clock. Tb represents the period of the data clock. As can be seenin FIG. 10, the edges of the clock CKQ lag behind by Tb/2 in comparisonwith the edges of the data signal. CKI is in phase with the data signal.The phase difference between CKQ and CKI is Tb/2. The resulting phasedifference pulses PD are negative. The length of these pulses is equalto Tb/2. Therefore the length of the signal PD represents the phasedifference between the reference clock CKQ and the data clock. SignalsERRQ and ERRI′ are identical. Consequently the output Pd, which is equalto ERRQ−2*ERRI′, corresponds to the signal ERRQ.

FIG. 11 shows another example of the signal generated by the circuitshown in FIG. 9. The transitions of the clock CKQ and the transitions ofthe signal data are synchronous, i.e. the data clock is in phase withthe clock CKQ. The output PD alternates between +1 and −1 in such a way,that the average output is 0. The integral over PD for a time period Tbis equal to 0. When data transmissions are missing, the output will be0. In this case, the transitions of the data signals are synchronouswith the transitions of CKQ.

If the clock CKQ is early, then a current output PD with a positiveaverage is generated. This is shown in FIG. 12. Again, when no datatransitions occur, the output is 0. FIG. 13 shows a second embodiment ofthe phase detector according to the present inventions. The referencesignal generators 40 and 42 shown in FIG. 13 are not the same as theones shown in FIG. 9. The exclusive OR-gates XOR are replaced byexclusive NOR-gates NXOR Furthermore the AND-gate in the output signalgenerator of the phase detector is replaced by a NOR-gate. A NOR-gate isconnected to the output of the reference signal generator 42 in FIG. 13.Both inputs of the NOR-gate connected to the output of the signalgenerator 42 have the same input. Therefore, the NOR-gate acts as aninverter.

The phase detector of FIG. 13 and the phase detector of FIG. 9 yield thesame output PD. The output PD of FIG. 9 is defined by the followingequation:PD=ERRQ−2(ERRQ×ERR)  (1)PD=(X _(1Q) ⊕X _(2Q))−2(X _(1Q) ⊕X _(2Q))×(X _(1I) ⊕X _(2I))  (2)PD=PD=(X _(1Q) ⊕X _(2Q))−2* (X _(1I) ⊕X _(2I)) + (X _(1Q) ⊕X ₂₁)  (3)

The phase detector of FIG. 13 is just the logical implementation ofequation (3). Therefore, FIGS. 10 to 12 also represent the signalsgenerated by the phase detector of FIG. 13.

The two NXOR circuits shown in FIG. 13 have a differential input and asingle ended output due to the specific implementation of the digitallogic function NXOR. The phase detector output PD will be directlyapplied to a loop filter. The subtraction circuit of the output signalgenerator 44 may be based on a linear amplifier. A phase locked looptransfer will have a finite amplitude at 0 Hertz. Therefore, the phaselocked loop will have a large static phase error, if implemented withthe phase detector of FIG. 13. In order to circumvent the abovementioned draw back, a third embodiment of the present invention isproposed and shown in FIG. 14.

The phase detector of FIG. 14 comprises a charge pump. Themultiplication and subtraction, which takes place in the multiplicatorand subtractor shown in FIGS. 9 and 13, now takes place in the chargepump of the output signal generator of FIG. 14. The advantage of theapproach is the integrator like loop transfer with the finite amplitudeof 0 Hertz. Hence, the static phase error will be dramatically reduced.The OR-gates of the output signal generator 44 have single a ended inputand a differential output. The differential output is needed by thedifferential type of charge pump. Two signals UP and DOWN are generatedfor driving the charge pump differentially. The differential output UPin FIG. 14 corresponds to signal ERRQ in FIG. 9 and the differentialoutput DOWN corresponds to signal ERRI′ in FIG. 9. The voltagedifferences transferred to the charge pump are converted into acorresponding current and the multiplication and subtraction of thecurrent is carried out by the charge pump.

FIGS. 13 and 14 each comprise a “dummy”-OR-gate. The dummy-OR-gate isconnected in both cases to the output of the respective second referencesignal generator 40. The dummy-OR-gate is needed in order to delay theoutput of the second reference signal generator 40, such that the secondand first reference signal generators 40 and 42 yield outputs having thesame delay.

A pure differential approach for the phase detector is also possible andthe embodiment of such a phase detector is shown in FIG. 15. Thisembodiment is based exclusively on differential XOR-gates anddifferential OR-gates. The outputs UP and DOWN are again a realisationof the logic equation (3). Similar to the phase detector of FIG. 14, thephase detector of FIG. 15 comprises a charge pump having two currentsources. The current source controlled by the UP signal is two timessmaller than the current source controlled by the down signal. Thisimplements the multiplication by two from FIGS. 9 and 13.

A fifth embodiment of the phase detector according to the presentinvention is shown in FIG. 16. The phase detector of FIG. 16 comprisesexclusively XOR-gates and D-latches. In a differential implementation,the same building blocks simplify the layout of the circuit. Anotheradvantage of using differential XORs consists in the particularimplementation of the XOR (the same holds for the OR) without stackingtransistors. When stacking transistors are used, source follower areneeded. The consequence is the amplitude reduction and speed penalty ofthe logic gate. This is the case of any implementation with theAND-gates.

The particularity of the phase detector of FIG. 16 is the fact, that thecurrent sources in the charge pump are identical and easy to match. Bothcurrent sources provide a current of I0. The XOR-gate for the downsignal has one input connected to 0 logic and an extra dummy XOR isadded at the input of the down XOR. The behaviour of the phase detectorcan be described by the following logic equation:PD=Up−Down  (4)Down=(X _(1I) ⊕X _(2I))=ERRI  (5)Up=(X _(1Q) ⊕X _(2Q))⊕(X _(1I) ⊕X _(2I))=ERRQ⊕ERRI  (6)

The equation (4) yields the same output signal as the equation (1)implemented by the phase detectors of FIGS. 9, 13, 14 and 15.

FIG. 17 shows eight different logical implementations PD1 to PD8 of thephase detector of FIG. 16. The logical implementation PD3 corresponds tothe logical implementation chosen for the phase detector of FIG. 16. PD3does not have differential inputs and outputs, but it is apparent to aperson skilled in the art, that exclusive OR-gates with differentialinputs and outputs may be used. The exclusive OR-gates providing anoutput DOWN and UP in PD3 correspond to the exclusive OR-gates in FIG.16 providing the outputs DOWN and UP. The exclusive OR-gate in PD3labeled with I and Q correspond to the exclusive OR-gates having theinputs X_(1L) and X_(2L) as well as the exclusive OR-gate having theinputs X_(1Q) and X_(2Q) respectively. The “dummy”-XOR-gate used in FIG.16 is not shown in PD3, since it is merely an advantageous but not anecessary component. The other logic implementations shown in FIG. 17 orconnected to the charge pump of FIG. 16 and the D-latches L1, L2, L3 andL4.

FIG. 18A shows an XOR-gate, which may be used in one of the previouslydiscussed embodiments of the present invention. The logic gate of FIG.18 has a first differential input A,Ā and a second differential inputB,B. The differential output of the gate is represented by Q, Q. Thedifferential XOR-gate of FIG. 18 further comprises eight transistors M1,M2, M3, . . . , M8. Furthermore, three current sources I01, I02 and I03are provided in the XOR-gate. Current source I01 connects thetransistors M1, M2 and M4 with ground. Current source I02 connectstransistors M3 and M5 with the ground and current source I03 connectstransistors M5, M7 and M8 with ground. Each of the inputs A,Ā, B and Bare connected to the gate of one of the transistors M1, M2, M7 and M8.The current sources I01, I02 and I03 each provide the same constantcurrent I0. The current sources added to the tails of the transistors M1to M8 allow the control of a swinging temperature and the control ofprocess variations by ensuring a constant voltage Io*R. R represents theresistors connected to the differential output Q, Q as well as theresistance of these resistors. A constant current source increases thesupply rejection with respect to ground and a constant supply current inthis positive supply. In a PLL-DCR configuration this is an importantadvantage since other building blocks like charge pumps and VCOs can bebuilt with less constraints for common mode signals.

FIG. 18B shows a logic table of the differential XOR-gate of FIG. 18Aand the analog values at the output of the XOR-gate. The differentialswing between logic states is I0*R. I0*R represents the voltagedifference at the differential output Q, Q. The common mode voltage VCOMshown in FIG. 18A is chosen a bit different from the common mode of thedifferential inputs. The transistors M3 and M6 are connected to the samecurrent source 02 and therefore, in the negative output, the constantcurrent is always present.

FIG. 19 shows a NXOR-gate having two differential inputs A, Ā′ and B, Band a single ended output Q. The differential inputs of the NXOR-gate ofFIG. 19 are each connected to a gate of one of the transistors M1, M2,M5 and M6 which are shown in FIG. 19. A common mode voltage VCOM isconnected to the gates of transistors M3 and M4 shown in FIG. 19. Afirst current source I01 is connected to transistors M1, M2 and M3. Asecond current source I02 is connected to transistors M4, M5 and M6.Current sources 101 and 102 both provide the same current I0. Thetransistors M3 and M4 are needed in order to keep the current source I01out of saturation, when both inputs A′ and B′ are low.

FIG. 20 shows a differential OR-gate which may be used in one of thephase detectors previously discussed. The differential OR-gate of FIG.20 comprises two differential inputs A, Ā and B, B as well as andifferential output Q, Q. Eight transistors M1 to M8 are provided in thedifferential OR-gate. Input A is connected to the gate of transistor M1,input B is connected to the gate of transistor M2. Transistors M1 and M2are both connected to the current source I01. The gates of transistorsM3 and M4 are each fed by common mode voltage VCOM. The sources anddrains of these transistors are connected to each other. Transistors M1,M2, M3 and M4 are each connected to the output Q. The differentialinputs Ā and B are connected to the gates of the transistors M7 and M8.Transistors M6, M7 and M8 are each connected to the current source I03.Transistor M6 has a common mode voltage VCOM at its gate. TransistorsM5, M6, M7 and M8 are each connected to the output Q. FIG. 20B shows alogical table of the differential OR-gate of FIG. 20A.

FIG. 21 shows an OR-gate which may also be used in each one of the phasedetectors previously discussed. The OR-gate of FIG. 21 has two singleended inputs A and B and a differential output Q, Q. Transistors M1, M2and M3 are provided in the OR-gate of FIG. 21. The gates of transistorsM1 and M2 form the inputs A and B respectively. The tails of thetransistors M1, M2 and M3 are each connected to a common current sourceI0. A common mode voltage VCOM forms the gate of transistor M3.

FIG. 22 shows a phase frequency detector comprising a phase detector 200and a frequency detector 210. The phase detector 200 in FIG. 21corresponds to the phase detector shown in FIG. 16. The reference clocksCKL and CKQ shown in FIG. 16 correspond to clock CKL/2 and CKQ/2 shownin FIG. 22 respectively. The frequency detector 210 has two referenceclocks CKQ and CKL. Clocks CKQ and CKL of the frequency detector 210 arequadrature clocks, i.e. they have the same frequency and are phaseshifted by T/4, wherein T is the period of the clocks. The frequencyf=1/T of the reference clock CKQ and CKL corresponds to the frequency ofthe data clock. The reference clock CKL/2 and CKQ/2 are also twoquadrature clocks having half the frequency of the data clock. Thefrequency detector 210 is a full rate frequency detector with tri-stateoutput. The phase detector is a half rate phase detector detector. Afrequency divider can generate two quadrature clocks CKI/2 and CKQ/2derived form one of the two quadrature clocks CKQ and CKL at full rate.The frequency detector 210 has two D-latches L1 and L2, the differentialoutput of which are connected to a MUX. This combination of D-latchesand MUX operates as a latch clocked on both UP and DOWN transitions ofthe data signal. Therefore, the data transitions sample two quadratureclock signals CKI and CKQ at full speed. The output of the MUX will beupdated only on the data transitions keeping the same error at theoutput between the transitions. Furthermore D-latches L3, L4 and anotherMUX form a similar combination of D-latches and MUX. The outputs of theMUX is shown in FIG. 22 have the reference signs PD_Q and PD_I. The PD_Qoutputs correspond to the outputs of the phase detector and the PD_Ioutputs are in quadrature with PD_Q. The phase difference between DATAand CKQ (respectively CKI) is transformed in a positive or negativequantized signal. When the signal is positive the clock will increaseits phase and for negative signals the clock will decrease its phase.

1. Phase Detector for detecting a phase difference between a data clock(DATA-CLK) and a reference clock (REF-CLK) using a data signal (DATA),wherein a transition of the data signal (DATA) is synchronous with atransition of the data clock (DATA-CLK) and the data clock (DATA-CLK)and the reference clock (REF-CLK) have the same frequency, comprising: afirst signal generator (42) for generating a first binary signal (ERRQ),a pulse width of which is equal to a first time difference (ΔT1) betweena transition of the data signal (DATA) and a transition of a firstreference clock signal (CKQ) adjacent to the transition of the datasignal (DATA), wherein the first signal generator comprises an input forreceiving the first reference clock signal (CKQ) and an input forreceiving the data signal (DATA), wherein the first reference clock(CKQ) has half the frequency of the reference clock (REF-CLK) and issynchronous with the reference clock, a second signal generator (40) forgenerating a second binary signal (ERRI), a pulse width of which isequal to a second time difference (ΔT2) between a transition of the datasignal (DATA) and a transition of the second reference clock signal(CKI) adjacent to the transition of the data signal (DATA), wherein thesecond signal generator (40) comprises an input for receiving the secondreference clock (CKI) and an input for receiving the data signal (DATA),output signal generator (44) for generating an output signalrepresentative of the phase difference between the data clock (DATA-CLK)and the reference clock (REF-CLK), wherein the output signal is equal toERRQ−2*(ERRQ AND ERRI) and AND represents a logical AND-operation, orthe output is equal to (ERRQ XOR ERRI)−ERRI, wherein XOR represents alogical XOR-operation.
 2. Phase detector for detecting a phasedifference according to claim 1, wherein the first signal generatorcomprises two D-latches that are both adapted to receive the data signal(DATA), a first one of the two D-latches of the first signal generatoris adapted to receive the first reference clock signal and a second oneof the two D-latches of the first signal generator is adapted to receivean inverted first reference clock.
 3. Phase detector for detecting aphase difference according to claim 2, wherein the second signalgenerator comprises two D-latches that are both adapted to receive thedata signal (DATA), a first one on the two D-latches of the secondsignal generator is adapted to receive the second reference clock and asecond one of the two D-latches of the second signal generator isadapted to receive an inverted second reference clock.
 4. Phase detectoraccording to claim 3, wherein signals output by the two D-latches of thefirst or second signal generator are either output to a XOR-gate or anXNOR-gate.
 5. Phase detector for detecting a phase difference accordingto claim 1, wherein the output signal generator (44) comprises anAND-gate having two inputs and an output, the inputs of the AND-gatereceive the first (ERRQ) and the second binary signal (ERRI), the outputsignal generator (44) comprises a multiplicator (*2) for multiplying theoutput of the AND-gate by 2, the output signal generator (44) comprisesa subtractor (SUM) for subtracting the output of the multiplicator (*2)from the first binary signal (ERRQ), said subtractor having an output(PD) representing the output of the phase detector.
 6. Phase detectoraccording to claim 1, wherein the output signal generator comprises afirst OR-gate (OR), wherein both inputs of the first OR-gate (OR) areconnected to the first binary signal (ERRQ), the output signal generatorcomprises a second OR-gate, wherein a first input of the second OR-gateis connected to the first binary signal (ERRQ) an a second input of thesecond OR-gate is connected to the second binary signal (ERRI), and theoutput signal generator comprises a charge pump connected to an outputof the first and second OR-gate (OR), the charge pump is adapted tomultiply the output of the second OR-gate by 2 and subtract the resultfrom the output of the first OR-gate.
 7. Phase detector according toclaim 1, wherein the output signal generator comprises a first XOR-gate,said first XOR-gate having an input receiving the first binary signal(ERRQ) and an input receiving the second binary signal (ERRI), theoutput signal generator comprises a second XOR-gate, said secondXOR-gate having an input receiving the second binary signal (ERRI) andan input receiving a logical 0, the output signal generator (ERRQ)comprises charge pump, said charge pump being adapted to subtract anoutput of the second XOR-gate from the output of the first XOR-gate. 8.Method for detecting a phase difference between a data clock (DATA-CLK)and a reference clock (REF-CLK) using a data signal (DATA), wherein atransition of the data signal (DATA) is synchronous with a transition ofthe data clock (DATA-CLK), comprising the steps of: receiving a firstreference clock signal (CKQ) and a second reference clock (CKI) signalboth having the same frequency (f) half as large as the frequency of thereference clock (REF-CLK), and a phase difference between the firstreference clock signal (CKQ) and the second reference clock signal (CKI)is equal to 1/(4f), generating a first binary signal (ERRQ), a pulsewidth of which is equal to a first time difference (ΔT1) between atransition of the data signal (DATA) and a transition of a firstreference clock signal (CKQ) adjacent to the transition of the datasignal (DATA), generating a second binary signal (ERRI), a pulse widthof which is equal to a second time difference (ΔT2) between a transitionof the data signal (DATA) and a transition of the second reference clocksignal (CKI) adjacent to the transition of the data signal (DATA),generating an output signal representative of the phase differencebetween the data clock (DATA-CLK) and the reference clock (REF-CLK),wherein the output signal is equal to ERRQ−2*(ERRQ AND ERRI) and ANDrepresents a logical AND-operation.